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Department of Electrical and Computer Engineering

Ziavras, Sotirios G.

Contact Info
Title: Professor & Associate Provost for Graduate Studies
Email: sotirios.g.ziavras@njit.edu
Office: Fenster Hall 145
Phone: 973-596-5651
Dept: Graduate Studies Office
Webpage: http://web.njit.edu/~ziavras

About Me

Dr. Sotirios G. Ziavras was born in Athens, Greece.

Dr. Ziavras received the Diploma in Electrical Engineering from the National Technical University of Athens (NTUA), Greece (1984), the M.Sc. degree in Electrical and Computer Engineering from Ohio University (1985), and the D.Sc. degree in Computer Science from George Washington University (1990). He graduated from NTUA in 9 semesters (normal duration of studies: 5 years/10 semesters).

He was a Graduate Teaching Assistant and a Research Assistant at Ohio University, and a Distinguished Graduate Teaching Assistant and a Research Assistant at George Washington University. He received an award from the Hellenic Government (IKY) in 1984 and the Richard E. Merwin Ph.D. Fellowship in 1986. From 1988 to 1989, he was also with the Computer Vision Laboratory of the Center for Automation Research at the University of Maryland in College Park, performing research in supercomputing techniques for parallel computer vision and numerical analysis (actual implementations on a Connection Machine supercomputer were also involved). He was with the RISO National Research Laboratory of Denmark in the summer of 1983, performing research in interactive computer graphics. He was a visiting Assistant Professor in the Electrical and Computer Engineering Department at George Mason University in the Spring of 1990. He joined the Electrical and Computer Engineering Department at NJIT in the Fall of 1990 as an Assistant Professor. He was promoted to Associate Professor in 1995 and then to Professor in 2001. He also holds a joint appointment in Computer Science.

He served as the Associate Chair for Graduate Studies in the ECE Department from 2001 to 2004 and again from 2007 to 2008.

Dr. Ziavras has served as an Associate Editor of the Pattern Recognition journal (1994-2006), and as a member of the Advisory Committee for the Computer and Information Science Section of the New York Academy of Sciences. He has been listed, among others, in

  • Who´s Who in Science and Engineering
  • Who´s Who in America
  • Who´s Who in the World
  • Who´s Who in the East
  • Who´s Who in American Education
  • Who´s Who in Engineering Education

He has authored about 140 papers. He is the Director of the Computer Architecture and Parallel Processing Laboratory (CAPPL).

He received a Research Initiation Award from the National Science Foundation in 1991. His research has been supported by the National Science Foundation (NSF), the Defense Advanced Research Projects Agency (DARPA), the New Jersey Commission on Science and Technology (NJCST), the U.S. Department of Energy (DOE), AT&T, NJIT, etc. He received in 1996 an NSF/DARPA (also sponsored by NASA) New Millennium Computing Point Design Studies grant for the design and feasibility analysis of a parallel computer that could achieve by the year 2005 near PetaFLOPS performance. He has served as a reviewer for many NASA and NSF proposals, and as a panel member for the evaluation of research proposals submitted to Federal Government agencies.

He has served as a program committee member for many international conferences He has presented about 40 invited seminars/talks at universities and scientific workshops.

He is a member of the IEEE (Senior member), Pattern Recognition Society, Greek Chamber of Engineers, and Eta Kappa Nu.

Education

  • National Technical University of Athens, Diploma, 1984.
  • Ohio University, M.S., 1985.
  • George Washington University, D.Sc., 1990.

 


Courses I Teach

COMPUTER SYSTEMS ARCHITECTURE
MASTER'S PROJECT
DOCTRL DISSRTN & RESEARCH
DOCTRL DISSRTN & RESEARCH

Selected Publications

  • J. Hu, S. Wang and S.G. Ziavras, “On the Exploitation of Narrow-Width Values for Improving Register File Reliability,” IEEE Transactions on VLSI Systems, accepted for publication.
  • X. Tang, C. Manikopoulos and S.G. Ziavras, “Generalized Anomaly Detection Model for Windows-Based Malicious Program Behavior,” International Journal of Network Security, Vol. 7, No. 3, Nov. 2008, pp. 437-444.
  • S. Wang, J. Hu and S.G. Ziavras, “Self-Adaptive Data Caches for Soft-Error Reliability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 8, August 2008, pp. 1503-1507.
  • D. Jin and S.G. Ziavras, "Robust Scalability Analysis and SPM Case Studies," The Journal of Supercomputing (full paper PDF), Vol. 43, No. 3, March 2008, pp. 199-223.
  • S. Wang, J. Hu and S.G. Ziavras, “BTB Access Filtering: A Low Energy and High Performance Design,” IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, 2008.
  • M.Z. Hasan and S.G. Ziavras, "Reconfiguration Framework for Multi-kernel Embedded Applications," 2nd Annual Reconfigurable and Adaptive Architectures Workshop (in conjunction with the 40th Annual IEEE/ACM International Symposium on Microarchitecture), Chicago, Illinois, December 2007.
  • S.G. Ziavras, A. Gerbessiotis and R. Bafna, "Coprocessor Design to Support MPI Primitives in Configurable Multiprocessors," Integration, the VLSI Journal (full paper PDF), Vol. 40, No.3, 2007, pp. 235-252.
  • H. Yang, S.G. Ziavras and J. Hu, "Reconfiguration Support for Vector Operations," International Journal of High Performance Systems Architecture, Vol. 1, No. 2, 2007, pp. 89 - 97.
  • M.Z. Hasan and S.G. Ziavras, "Resource Management for Dynamically-Challenged Reconfigurable Systems," 12th IEEE Conference on Emerging Technologies and Factory Automation, 2007, pp. 119-126.
  • X. Wang, S.G. Ziavras and J. Hu, “Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors,” International Conference on Engineering of Reconfigurable Systems and Algorithms, June 25-28, 2007.
  • H. Yang, S. Wang, S.G. Ziavras and J. Hu, “Vector Processing Support for FPGA-Oriented High Performance Applications,” IEEE Computer Society Annual Symposium on VLSI, May 9-11, 2007.
  • X. Wang, S.G. Ziavras, et al, “Parallel Solution of Newton’s Power Flow Equations on Configurable Chips,” International Journal of Electrical Power and Energy Systems (full paper PDF), Vol. 29, No. 5, June 2007, pp. 422-431.
  • S. Wang, H. Yang, J. Hu and S.G. Ziavras, “Asymmetrically Banked Value-Aware Register Files,” IEEE Computer Society Annual Symposium on VLSI, May 9-11, 2007.
  • Click here for full list of Publications