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Department of Electrical and Computer Engineering

Ziavras, Sotirios G.

Contact Info
Title: Professor & Associate Provost for Graduate Studies
Email: sotirios.g.ziavras@njit.edu
Office: Fenster Hall 145
Phone: 973-596-3579
Dept: Graduate Studies Office
Webpage: http://web.njit.edu/~ziavras

About Me

Dr. Ziavras received the Diploma in Electrical Engineering from the National Technical University of Athens (NTUA), Greece, the M.Sc. degree in Electrical and Computer Engineering from Ohio University, and the D.Sc. degree in Computer Science from George Washington University. He graduated from NTUA in 9 semesters (normal duration of studies: 5 years/10 semesters).

He was a Graduate Teaching Assistant and a Research Assistant at Ohio University, and a Distinguished Graduate Teaching Assistant and a Research Assistant at George Washington University. He received an award from the Hellenic Government (IKY) in 1984 and the Richard E. Merwin Ph.D. Fellowship in 1986. From 1988 to 1989, he was also with the Computer Vision Laboratory of the Center for Automation Research at the University of Maryland in College Park, performing research in supercomputing techniques for parallel computer vision and numerical analysis (actual implementations on a Connection Machine supercomputer were also involved). He was with the RISO National Research Laboratory of Denmark in the summer of 1983, performing research in interactive computer graphics. He was a visiting Assistant Professor in the Electrical and Computer Engineering Department at George Mason University in the Spring of 1990. He joined the Electrical and Computer Engineering Department at NJIT in the Fall of 1990 as an Assistant Professor. He was promoted to Associate Professor in 1995 and then to Professor in 2001. He served in the past as the Associate Chair for Graduate Studies in the ECE Department (2001-2004, 2007-2008).

He currently serves as NJIT’s Associate Provost for Graduate Studies.

He has served as an Associate Editor, among others, of the Pattern Recognition journal (1994-2006), and as a member of the Advisory Committee for the Computer and Information Science Section of the New York Academy of Sciences. He is listed in several who’s who publications, such as:

  • Who´s Who in Science and Engineering
  • Who´s Who in America
  • Who´s Who in the World
  • Who´s Who in the East
  • Who´s Who in American Education
  • Who´s Who in Engineering Education

He has authored about 180 papers. He is the Director of the Computer Architecture and Parallel Processing Laboratory (CAPPL).

He received a Research Initiation Award from the National Science Foundation in 1991. His research has been supported by the National Science Foundation (NSF), the Defense Advanced Research Projects Agency (DARPA), the New Jersey Commission on Science and Technology (NJCST), the U.S. Department of Energy (DOE), AT&T, NJIT, etc. He received in 1996 an NSF/DARPA (also sponsored by NASA) New Millennium Computing Point Design Studies grant for the design and feasibility analysis of a parallel computer that could achieve by the year 2005 near PetaFLOPS performance. He has served as a reviewer for many NASA and NSF proposals, and as a panel member for the evaluation of research proposals submitted to Federal Government agencies.

He frequently serves as a program committee member for international conferences. He has presented about 40 invited seminars/talks at universities and scientific workshops.

He is a member of the IEEE (Senior member), Pattern Recognition Society, Greek Chamber of Engineers, and Eta Kappa Nu.

 

Education

  • National Technical University of Athens, Diploma, 1984.
  • Ohio University, M.S., 1985.
  • George Washington University, D.Sc., 1990.

 


Courses I Teach

COMPUTER SYSTEMS ARCHITECTURE
DOCTRL DISSRTN & RESEARCH
DOCTRL DISSRTN & RESEARCH

Research Interests

Dr. Ziavras focuses on Advanced Computer Architecture, Parallel Processing, Multicore Processors, Heterogeneous Multiprocessors, System-on-Chip (SoC) designs, Reconfigurable Computing, Field-Programmable Gate Arrays (FPGAs) and Image Processing.


Selected Publications

  • S.F. Beldianu and S.G. Ziavras, “Performance-Energy Optimizations for Shared Vector Accelerators in Multicores,” IEEE Transactions on Computers, accepted for publication (DOI:10.1109/TC.2013.2295820).
  • S.F. Beldianu and S.G. Ziavras, “ASIC Design of Shared Vector Accelerators for Multicore Processors,” The 26th International Symposium on Computer Architecture and High Performance Computing, October 2014.
  • K.M. Salehin, R. Rojas-Cessa, and S.G. Ziavras, "A Method to Measure Packet Processing Time of Hosts using High-Speed Transmission Lines," IEEE Systems Journal, 2014.
  • S.F. Beldianu and S.G. Ziavras, “Multicore-based Vector Coprocessor Sharing for Performance and Energy Gains,” ACM Transactions on Embedded Computing Systems, Special Issue on Application Specific Processors, Vol. 13, No. 2, September 2013, pp. 17:1-17:25.
  • S. Suresh, S.F. Beldianu and S.G. Ziavras, “FPGA and ASIC Square Root Designs for High Performance and Power Efficiency,” 24th IEEE International Conference on Application-specific Systems, Architectures and Processors, June 2013.
  • Sajid, M.M. Ahmed and S.G. Ziavras, “Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm,” Journal of Signal Processing Systems, Vol. 67, No. 2, May 2012, pp. 157-166.
  • S. Wang, J. Hu and S.G. Ziavras, “Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, April 2012, pp. 643-654.
  • N.B. Guinde and S.G. Ziavras, “Efficient Hardware Support for Pattern Matching in Network Intrusion Detection,” Computers and Security (The official journal of Technical Committee 11 (computer security) of the International Federation of Information Processing), Volume 29, No. 7, October 2010, pp. 756-769.
  • S. Motahari, S. Ziavras and Q. Jones, "Online Anonymity Protection in Computer-Mediated Communication,” IEEE Transactions on Information Forensics & Security, Vol. 5, No. 3, September 2010, pp. 570-580.
  • S. Wang, J. Hu and S.G. Ziavras, “On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors,” IEEE Transactions on Computers, Vol. 58, No. 9, September 2009, pp. 1171-1184.
  • J. Hu, S. Wang and S.G. Ziavras, “On the Exploitation of Narrow-Width Values for Improving Register File Reliability,” IEEE Transactions on VLSI Systems, Vol. 17, No. 7, July 2009, pp. 953-963.
  • D. Jin and S.G. Ziavras, "Robust Scalability Analysis and SPM Case Studies," The Journal of Supercomputing, Vol. 43, No. 3, March 2008, pp. 199-223.
  • S.G. Ziavras, A. Gerbessiotis and R. Bafna, "Coprocessor Design to Support MPI Primitives in Configurable Multiprocessors," Integration, the VLSI Journal , Vol. 40, No.3, 2007, pp. 235-252.
  • X. Wang, S.G. Ziavras, et al, “Parallel Solution of Newton’s Power Flow Equations on Configurable Chips,” International Journal of Electrical Power and Energy Systems, Vol. 29, No. 5, June 2007, pp. 422-431.
  • D. Jin and S.G. Ziavras, "Modeling Distributed Data Representation and its Effect on Parallel Data Accesses," Journal of Parallel and Distributed Computing, Special Issue on Design and Performance of Networks for Super-, Cluster-, and Grid-Computing, Vol. 65, No. 10, October 2005, pp. 1281-1289.
  • D. Jin and S.G. Ziavras, "A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters," IEEE Transactions on Parallel and Distributed Systems, Vol. 15, No. 9, September 2004, pp. 783-794.
  • X. Wang and S.G. Ziavras, "Parallel LU Factorization of Sparse Matrices on FPGA-Based Configurable Computing Engines," Concurrency and Computation: Practice and Experience, Vol. 16, No. 4, April 2004, pp. 319-343.
  • S.G. Ziavras and A. Mukherjee, ``Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduced Hypercube Parallel Computers,´´ Parallel Computing, Vol. 22, 1996, pp. 595-606.
  • S.G. Ziavras, ``RH: A Versatile Family of Reduced Hypercube Interconnection Networks,´´ IEEE Transactions on Parallel and Distributed Systems, Vol. 5, No. 11, Nov. 1994, pp. 1210-1220.

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