Abstract:

Hf-silicate based oxides are among the leading candidates to be included into the first generation of high-? gate stacks in nanoscale CMOS technology because of its distinct advantages as far as thermal stability, leakage characteristics, threshold instability and mobility degradation are concerned. Although the CMOS process compatibility of TiN/HfSixOy (20% SiO2) has been achieved, its reliability, which is limited by trapping at pre-existing and stress induced defects within the bulk high-?, remains to be a major concern.

Energy levels of the electrically active ionic defects within the bulk high-? have been experimentally observed in the context of MOS band diagram for the first time in our gate stacks from low temperature and leakage measurements. Excellent match between experimental and calculated defect levels shows that bulk O vacancies are probably responsible for electron trapping at both shallow and deep levels. Their role in trapping and transport under different gate polarity and band bending conditions has been determined. For gate injection, electron transport through mid-gap states dominates, which leads to slow transient trapping at deep levels. Under substrate injection, depending on bias condition, field and temperature dependent transport through conduction-edge shallow levels or trap-assisted tunneling due to negative-U transition occurs. The former gives rise to fast transient trapping, whereas the latter is responsible for slow transient trapping.

We observed mixed degradation, due to trapping of both electrons and holes in the experimentally observed deep levels within the bulk high-K, under constant voltage stress (CVS) applied on n-channel MOS capacitors with negative bias condition. Mixed degradation resulted in turn-around effect in flat-band voltage shift (?VFB) with respect to  stress time.  Under CVS with positive bias, applied on nMOSFETs, lateral distribution of trapped charges in the deep levels causes turn-around effect in threshold voltage shift (?VT) with respect to stress levels.   

Initial results from negative bias temperature instability (NBTI) studies under low bias conditions at elevated temperatures show that interface state generation in pMOSFETs is quite low and ?VT is dominated by mixed degradation. However, significant interface state generation induced ?VT was observed for high bias conditions.

In this proposal we plan to analyze the initial NBTI results and continue to carry out experiments involving time dependent dielectrics breakdown (TDDB) and deep level transient spectroscopy (DLTS) to further confirm our assertion of the already obtained results on trap behavior and their energy levels in TiN/HfSixOy gate stacks.

Committee Members:

Dr. Durgamadhab Misra, Advisor, Professor, Department of ECE, Advisor, NJIT.

Dr. Arvind Kumar, IBM Thomas J Watson Research Center, Yorktown Heights NY

Dr. Leonid Tsybeskov, Associate Professor, Dept. of ECE, Committee Member, NJIT.

Dr. Marek Sosnowski, Professor, Dept. of ECE, Committee Member, NJIT.

Dr. Anthony Fiory, Research Professor, Dept of Physics, Committee Member, NJIT.

Dr. N.M. Ravindra, Professor, Dept of Physics, Committee Member, NJIT.