The ITRS roadmap clearly outlines the necessity to implement high-? dielectrics for sub 45 nm technology nodes and there is a clear trend that Hf-based dielectrics will play a dominant role. However, in order to overcome the associated mobility degradation compared to SiO2, gate stacks based on FUSI or metal gate electrodes are gaining high interest.  In recent years it has become obvious that low frequency noise diagnostics is a powerful tool for device performance and reliability characterization. For deep sub micron technologies a low 1/f noise value is essential for both analog and digital applications.  Less information is available on the low frequency noise performance of these gate stacks. 

This proposal demonstrates the necessity of gate stack engineering for achieving a low 1/f noise performance. The impact of several gate processing parameters, such as thickness of the interfacial layer and the high-? oxide, bulk properties of the high-? layer, high-k deposition technique, percentage of hafnium content, post deposition anneal (PDA) treatments, choice of gate electrode material (poly-silicon, fully silicided or metal), gate electrode processing is investigated in detail and the role of the different interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. Such a systematic study will form the basis for noise modeling as for these gate-dielectrics the standard noise models is no longer applicable. 

Committee Members:

Dr. Durgamadhab Misra, Department of ECE, Advisor, NJIT.

Dr. Cor Claeys, Co-Advisor, ESAT, KUL/IMEC, Belgium.

Dr. Leonid Tsybeskov, Dept. of ECE, Committee Member, NJIT.

Dr. Marek Sosnowski, Dept. of ECE, Committee Member, NJIT.

Dr. Trevor Tyson, Dept of Physics, Committee Member, NJIT.