Abstract

As VLSI technology continues scaling down, the increasing energy consumption has become a major constraint in designing both low-end and high-end microprocessors. Caches are one of the most important components in processors that bridge the speed gap between processor datapath and main memory. They contribute to a significant portion of chip area and energy consumption. In particular, cache leakage consumption is expected to exceed dynamic energy in 70nm technology.

In this talk, I will present my recent efforts in reducing cache dynamic and leakage energy. First, I will introduce a compiler infrastructure to automatically analyze the data reuse patterns of embedded applications, determine the optimal data cache configurations for different code sections, and insert instructions in the code to initiate cache reconfigurations at runtime.

In the second part of my talk, I will cover two schemes for optimizing the leakage energy in instruction caches. The first scheme uses static compiler analysis to extract instruction lifetimes and turns off the cache lines that hold dead instructions. In comparison, the second scheme utilizes program phase information to dynamically identify the cache hotspots in execution for leakage control. I will report results from my experimental evaluation of both the techniques.

Biography

Jie Hu received his B.E. degree in computer science and engineering from Beijing University of Aeronautics and Astronautics, China, in 1997 and his M.E. degree in signal and information processing from Peking University, China, in 2000. He is currently a Ph.D. candidate in computer science and engineering at the Pennsylvania State University. His research interests are in the areas of computer architecture, compiler, low power systems design, and power-efficient reliable systems design.