Abstract:

Hafnium Oxide based high-k (high dielectric constant) gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal oxide semiconductor (CMOS) technology, specifically in the area of low power applications. Because high-k gate dielectrics can be several times thicker, they reduce the gate leakage by over 100 times while keeping the device performance intact. The next generation of transistors (45nm and beyond) with high-k dielectric has an interfacial layer (typically SiO2) between high-k and the substrate. To incorporate high-k in CMOS devices, reliability studies need to be done systematically for high-k layer and interfacial SiO2 layer. The soft spot in leading breakdown (BD) mechanisms in high-k/interfacial layer (IL)/metal gate stack has been claimed to be trap generation in the interfacial SiO2 layer. But to understand the breakdown characteristics of high-k/SiO2 gate stack completely, it is important to study separately the role of SiO2 interfacial layers and bulk high-k gate dielectrics without any interfacial layer, while maintaining same growth conditions.

In this proposal it is planned to undertake a comparative study of the individual breakdown characteristics of HfO2 and in-situ steam generated (ISSG)-SiO2 MOS structures to high-k/IL (ISSG SiO2)/metal gate stack. Initial results indicates that after constant voltage stress, identical soft breakdown and stress-induced leakage current (SILC) degradation were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only metal-insulator-metal (MIM) capacitors showed insignificant SILC and soft breakdown until it went into hard breakdown. Based on observed gate current with stress time (Ig-t), SILC and charge-to-breakdown (QBD), we believe that breakdown of interfacial layer contributes to the breakdown of metal gate/high-κ/SiO2/Si gate stacks at room temperature.

It is advantageous to investigate and understand the effect of temperature on breakdown characteristics. It would help projection of reliability from the statistical data collected at accelerated temperatures. Initially, TDDB characteristics of the same gate stack (TiN/HfO2/ISSG-SiO2/p-Si) were investigated at elevated temperature in this research. The normalized SILC shows power-law dependence with stress time at high temperature. The exponent in power law dependence seems to be sensitive to stress temperature. The stress time dependent normalized SILC (ΔJg/Jg0) and activation energy extracted from Weibull distribution of the time-to-breakdown data show IL initiates the gate stack breakdown at higher temperatures as well. The Weibull slope, β increases with temperature for the gate stack and HfO2-only MIM capacitors. Therefore, it can be added that the breakdown of the high-k layer ultimately determines the breakdown of the gate stack during substrate injection at elevated temperature. The proposed work includes stress polarity dependence of breakdown, low-voltage-SILC analysis and correlating negative bias temperature instability (NBTI) and TDDB for a comprehensive breakdown mechanism.

Committee Members:

Dr. Durgamadhab Misra (Advisor), Professor of Electrical and Computer Engineering Dept, NJIT
Dr. Haim Grebel, Professor of Electrical and Computer Engineering Dept, NJIT
Dr. Marek Sosnowski, Professor of Electrical and Computer Engineering Dept, NJIT
Dr. Leonid Tsybeskov, Professor of Electrical and Computer Engineering Dept, NJIT
Dr. Roland A. Levy, Distinguished Professor of Physics Dept, NJIT.

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Note: All MS thesis and PhD dissertation (proposal) defense are counted towards ECE791.