Hongyan Yang, NJIT
Date: October 23, 2007 (Tuesday)
Time: 3:30 PM
Location: ECE 202, NJIT

Abstract:

It recently became increasingly difficult to build higher speed uniprocessor chips because of performance degradation and high power consumption. The quadratically increasing circuit complexity forbade the exploration of more instruction-level parallelism (ILP). To continue raising the performance, silicon designers have recently looked at thread-level parallelism (TLP) to realize a new architecture design paradigm. Multicore processor design is the result of this trend . It has proven quite capable in performance increase and provides new opportunities in power management and system scalability. But current multicore processors do not provide powerful vector architecture support which could yield significant speedups to array operations while maintaining area/power efficiency.

This thesis proposes and presents the realization of an FPGA-based prototype for multicore processors with a shared vector unit (MCwSV). The idea is that rather than improving only scalar or TLP performance, some hardware budget could be used to realize a vector unit to greatly speedup applications abundant in data- level parallelism. To be realistic, limited by the parallelism in the application itself and by the compiler's vectorizing abilities, most of the general-purpose programs can only be partially vectorized. Thus, for efficient resource usage, one vector unit should be shared by several scalar processors. This approach could also preserve the overall budget within acceptable limits.

The design, implementation and evaluation of an MCwSV system with two scalar processors and a shared vector unit are presented in this thesis. The MicroBlaze processor, which is a commercial IP (Intellectual Property) core from Xilinx, is used as the scalar processor; in our experiments our own designed vector unit is connected to a pair of MicroBlaze processors through stand bus interfaces. The overall system is organized in a decoupled manner with a multi-banked memory structure. This decoupled organization along with the multi- bank structure provides substantial system scalability. The vector unit can be easily configured to contain various types and numbers of function units, and various vector register and element sizes to match the specific requirements of applications. For a given area budget, benchmarking with applications from various domains shows that the MCwSV system can provide significant performance increase as compared to a multicore system without a vector unit.

This work will also eventually focus on implementations on Xilinx FPGAs, so the benefits of this design paradigm in the framework of configurable computing is evaluated as well. The analysis shows that the flexibility inherent in configurable systems aids the task of matching better given applications.

Committee Members:

Dr. Sotirios G. Ziavras (Advisor), Professor, ECE Dept., NJIT

Dr. Edwin Hou, Associate Professor, ECE Dept., NJIT

Dr. Jie Hu, Assistant Professor, ECE Dept., NJIT

Dr. Roberto Rojas-Cessa, Associate Professor, ECE Dept., NJIT

Dr. Alexandros V. Gerbessiotis, Associate Professor, CS Dept, NJIT

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Note: All ECE MS thesis defense and Ph.D. dissertation (proposal) defense are counted towards ECE791.