By: Xiaofang Wang
Advisor: Sotirios G. Ziavras
Department of Electrical and Computer Engineering

Time: 11:00 AM, Wednesday, December 7th, 2005.
Place:  Room 202, ECE Center, New Jersey Institute of Technology, Newark NJ. Directions

Abstract

Most FPGA (Field-Programmable Gate Array)-based custom reconfigurable computing machines are Application-Specific Programmable Circuits (ASPCs) that are developer programmable instead of user programmable. The major disadvantages of ASPCs are minimal programmability, and significant time and energy overheads caused by required hardware reconfiguration when the problem size outnumbers the available resources; these problems are expected to become more serious with increases in the FPGA chip size. On the other hand, dominant high-performance computing systems suffer from high communication latencies and/or scalability problems.

This research introduces low-cost, user-programmable and reconfigurable MultiProcessor-on-a-Programmable-Chip (MPoPC) systems for high-performance, low-cost computing. It also proposes a relevant resource management framework that deals with performance, power consumption and energy issues. These semi-customized systems reduce significantly the need for runtime device reconfiguration by employing user-programmable processing elements that are reusable for different tasks in large, data-parallel applications. For the sake of illustration, two different types of MPoPCs with hardware FPUs (floating-point units) are designed and implemented for credible performance evaluation and modeling: the coarse-grain MIMD (Multiple-Instruction, Multiple-Data) CG-MPoPC machine based on a processor IP (Intellectual Property) core and the mixed-mode (MIMD, SIMD or M-SIMD) variant-grain HERA (HEterogeneous Reconfigurable Architecture) machine. Two common computation-intensive benchmark algorithms, matrix-matrix multiplication (MMM) and LU factorization are studied, and their parallel solution is shown for the two MPoPCs. The performance is evaluated with large sparse real-world matrices primarily from power engineering.  The largest advantage of reconfigurable logic lies in its large degree of hardware customization and reconfiguration which allows reusing the resources to match the computation and communication needs of the applications. Therefore, a major effort in the presented design methodology for mixed-mode MPoPCs, like HERA, is devoted to effective resource management. A two-phase approach is proposed. At compile time, an architecture is customized and synthesized for the application using an Integer Linear Programming (ILP) formulation and a parameterized hardware component library. Various run-time scheduling schemes with different performance-energy objectives are proposed for the second phase. A system-level energy model for HERA, which is based on low-level implementation data and run-time statistics, is proposed to guide us in performance-energy trade-off decisions.

Committee Members:
Sotirios G. Ziavras, Advisor, Professor, ECE Dept., NJIT
Alexandros V. Gerbessiotis, Associate Professor, CS Dept., NJIT
Jie Hu, Assistant Professor, ECE Dept., NJIT
Durgamadhab Misra, Professor, ECE Dept., NJIT
Roberto Rojas-Cessa, Assistant Professor, ECE Dept., NJIT